1. Field of the Invention
The present invention relates to a semiconductor chip that has a plurality of pins serving as signal input/output terminals.
2. Description of the Background Art
FIG. 9 is a diagram showing the structure of a common semiconductor chip that includes logic circuitry, memory circuitry, etc. This semiconductor chip CP includes core circuitry CR that provides logical and memory functions for processing and storing signals and an input/output controller IOC for coordinating the input/output of the signals. The semiconductor chip CP is also provided with a large number of pins PN located along its periphery and serving as signal input/output terminals.
The input/output controller IOC includes an input/output buffer BF and a setting memory STM. The input/output buffer BF times and coordinates the transfer of signals between the core circuitry CR and the pins PN, i.e. an input signal Din to the core circuitry CR and an output signal Dout from the core circuitry CR. The setting memory STM, formed of a register, is a storage area for storing settings for the control of input/output signals by the input/output buffer BF.
Now, when a semiconductor chip is encapsulated, e.g. with resin, and packaged, all pins on the semiconductor chip may or may not be connected to external lead terminals of the package.
FIG. 10 is a diagram that shows a simple example of the packaging of a semiconductor chip, where a semiconductor chip CPa has eight pins that are all connected to the external lead terminals of the package. On the other hand, FIG. 11 shows an example in which some of the pins of the same semiconductor chip CPa are not connected to external lead terminals of the package.
In FIG. 10, pins PN1 to PN8 on the semiconductor chip CPa are respectively connected to external lead terminals LD1 to LD8 of the package PKa through bonding wires WB1 to WB8.
On the other hand, in FIG. 11, the pins PN1 to PN3 and PN6 to PN8 on the semiconductor chip CPa are respectively connected to the external lead terminals LD1 to LD3 and LD6 to LD8 of the package PKb through bonding wires WB1 to WB3 and WB6 to WB8, but the package PKb does not have bonding wires and external lead terminals for the fourth pin PN4 and the fifth pin PN5. That is to say, the fourth pin PN4 and the fifth pin PN5 are dead (unconnected) pins that are not used.
In general, a semiconductor chip CPa often has such dead pins, depending on its use. For example, when specifications drawn up by one customer need the fourth and fifth pins PN4 and PN5 but specifications by another customer do not need the fourth and fifth pins PN4 and PN5, it is a common practice to deliver the same semiconductor chips CPa enclosed in the package PKa of FIG. 10 and the package PKb of FIG. 11 respectively to the two customers. The package PKb of FIG. 1, which has no unnecessary external lead terminals, can be smaller in size than the package PKa of FIG. 10.
Now, the input/output buffer BF sets the directions of signals at individual pins on the basis of the contents stored in the setting memory STM, so as to determine whether the individual pins on the semiconductor chip serve as input pins for receiving input signals from the outside or as output pins for extracting output signals to the outside. The input/output buffer BF has a mechanism, for each pin, to set the signal direction.
FIG. 12 is a diagram showing an example of the signal direction setting mechanism in a conventional input/output buffer BFe, where, among the pins PN1 to PN8 on the semiconductor chip CPa, the fourth pin PN4 and the fifth pin PN 5 are shown with their respective mechanisms.
For example, the signal direction setting mechanism for the fourth pin PN4 includes a 3-state buffer TB4 and a transfer gate TG4.
The 3-state buffer TB4 receives an output signal Dout from the core circuitry CR at its input end, and its output end is connected to the fourth pin PN4. Also, information stored in the setting memory STMe is given as a signal SG4c, e.g. logically inverted, to the enable end of the 3-state buffer TB4.
The input end of the transfer gate TG4 is connected to the fourth pin PN4 and its output end outputs an input signal Din to the core circuitry CR. The signal SG4c is given to the gate of the N-channel MOS transistor of the transfer gate TG4, and also to the gate of the P-channel MOS transistor of the transfer gate TG4 through an inverter IV4.
The signal SG4c is applied to both of the 3-state buffer TB4 and the transfer gate TG4 as shown above, and then it can be determined whether to make the fourth pin PN4 function as an input pin or an output pin, depending on whether the signal SG4c is High or Low. That is to say, the fourth pin PN4 functions as an input pin when the signal SG4c is High, and it functions as an output pin when the signal SG4c is Low.
A similar signal direction setting mechanism is provided also for the fifth pin PN5, where information stored in the setting memory STMe is given as a signal SG5c to both of a 3-state buffer TB5 and a transfer gate TG5. While FIG. 12 only shows signal direction setting mechanisms associated with the pins PN4 and PN5, it is understood that similar mechanisms (not shown) are provided also for other pins PN1 to PN3, PN6 to PN8.
FIG. 13 is a diagram illustrating the contents stored in a memory table MTe contained in the setting memory STMe. The memory table MTe stores data about signal input/output directions at the pins PN1 to PN8, as well as other information (not shown) such as control data for an input/output control register (not shown) provided in the semiconductor chip CPa. Such memory table MTe is called SFR (Special Function Register), for example.
For instance, the data ST4 about the signal direction at the fourth pin PN4 includes bit data Sin4 in which a flag is set ON when the fourth pin PN4 should function as an input pin and bit data Sout4 in which a flag is set ON when the fourth pin PN4 should function as an output pin. Similarly, the data ST5 about the signal direction at the fifth pin PN5 includes bit data Sin5 and Sout5.
It is then determined, depending on the states of the flags in the bit data Sin4 and Sout4, whether the signal SG4c given to the 3-state buffer TB4 and the transfer gate TG4 associated with the fourth pin PN4 should be High or Low. That is to say, when the flag in the bit data Sin4 is ON and the flag in the bit data Sout4 is OFF, then the signal SG4c is High and the fourth pin PN4 functions as an input pin. On the other hand, when the flag in the bit data Sin4 is OFF and the flag in the bit data Sout4 is ON, then the signal SG4c is Low and the fourth pin PN4 functions as an output pin.
The same applies to the signal SG5c for the fifth pin PN5, and also to other pins PN1 to PN3 and PN6 to PN8.
Such signal direction setting mechanisms can thus specify whether to make the individual pins PN1 to PN8 serve as input pins or output pins.
When a pin is dead (not connected) and functions as an input pin, then the potential at the dead pin comes in a floating state, so that the signal level, High or Low, cannot be determined. This may cause malfunctions of the core circuitry CR.
Accordingly, in the memory table MTe of FIG. 13, the flags in the bit data Sin4 and Sout4 must be properly set so that the dead pin functions as an output pin. That is, when the dead pin functions as an output pin, then the potential is fixed at the potential of a signal generated in the core circuitry CR (either High or Low). Such potential control for dead pins is generally referred to as xe2x80x9cdead pin potential control process.xe2x80x9d
However, the setting of data in the memory table MTe for specifying the input/output directions of signals at the individual pins PN1 to PN8 is done by the customer to which the semiconductor chip CPa has been delivered. When the fourth pin PN4 and the fifth pin PN5 are used as dead pins in the package PKa shown in FIG. 10, the customer can easily notice that the two pins are dead pins. That is to say, the presence of the external lead terminals LD4 and LD5 allows the customer to readily notice the presence of the fourth and fifth pins PN4 and PN5 within the semiconductor chip CPa.
On the other hand, with the package PKb of FIG. 11, it is difficult for the customer to notice that the fourth pin PN4 and the fifth pin PN5 are dead pins. That is, the customer may fail to notice the presence of the fourth and fifth pins PN4 and PN5 within the semiconductor chip CPa because it has no external lead terminals associated with the fourth and fifth pins PN4 and PN5.
Thus, in the memory table MTe, data about signal input/output directions at individual pins PN1 to PN8 is likely to be set improperly, especially with packages like the package PKb shown in FIG. 11. That is, even when the memory table MTe includes items for setting data about the signal input/output directions at the individual pins, the customer may fail to notice them, or may set data inadequately, since the presence of the fourth pin PN4 and the fifth pin PN5 within the semiconductor chip CPa is not easy to notice for the customer. Then dead pins may function as input pins, possibly causing malfunctions of the core circuitry CR.
An object of the present invention is to provide a semiconductor chip with which presence of dead pins can be readily noticed and a dead pin potential control process can be performed easily.
According to an aspect of the present invention, a semiconductor chip includes a plurality of pins, core circuitry, and an input/output controller. The plurality of pins serve as input/output terminals for signals, the core circuitry processes or stores the signals, and the input/output controller controls the input/output of the signals through the pins.
At least one of the plurality of pins is a dead pin which is not used. The input/output controller has a storage area for storing settings for controlling the input/output of the signals, and the storage area contains, as one of the settings, a first item for specifying whether a given potential should be applied to the at least one dead pin, and the semiconductor chip further includes a switch capable of applying the given potential to the at least one dead pin in accordance with the content of the first item.
The storage area in the input/output controller stores, as one of the settings, a first item for specifying whether or not to apply a given potential to at least one dead pin and a given potential can be applied to the at least one dead pin in accordance with the content of the first item. This provides a semiconductor chip with which the presence of dead pins can be easily noticed and a dead pin potential control process can be performed easily.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.